1. Field of the Invention
This invention relates to antifuses, and in particular to an antifuse structure with an increased breakdown at the edges of an antifuse layer.
2. Description of the Related Art
Antifuses are well known in the art. An antifuse is a structure which is non-conductive when manufactured, but becomes permanently conductive by applying a predetermined voltage across its terminals. Antifuses are typically used in programmable logic devices to programmably interconnect conductive lines.
FIGS. 1A-1D illustrate a conventional method of forming an antifuse. Referring to FIG. 1A, a polycrystalline silicon layer 11 is formed on substrate 10 to provide a lower conductive terminal for the antifuse. An insulation layer 13 is then deposited and patterned to partially expose polycrystalline silicon layer 11 as shown in FIG. 1B. Referring to FIG. 1C, an amorphous silicon layer 14 is then deposited and patterned to cover the exposed portion of polycrystalline silicon layer 11 and portions of insulation layer 13 adjacent to polycrystalline silicon layer 11. Referring to FIG. 1D, conductive layers 18, including titanium layer 15, titanium nitride layer 16, and aluminum-silicon layer 17, are formed over amorphous silicon layer 14, and then patterned (not shown) to form an upper conductive terminal.
However, antifuse 20 requires a relatively high voltage, typically 12-14 volts, to program. Standard transistors used in 5-volt integrated circuit systems typically break down between 12-14 volts. Thus, special processing is needed to enhance the breakdown characteristic of the transistors for programming the antifuse. Moreover, to ensure proper operation of the integrated circuit system, other structures in the system must be isolated from the antifuse programming voltages.
Furthermore, antifuse 20 is undesirably affected by internal temperatures generated during programming. Specifically, during programming of antifuse 20, the leakage current of this device increases with the increase in applied voltage. Eventually, the leakage current focuses on a localized weak spot in amorphous silicon layer 14. A thermal runaway condition then develops which results in localized heating and, eventually, filament formation between the upper conductive terminal and the lower conductive terminal. The different thermal expansion coefficients of the materials in different layers of the antifuse structure in turn cause stresses to develop in the material as it cools after programming. Over time, these stresses will relax, producing movement between layers of the antifuse material.
FIG. 2A shows a partial top view of antifuse 20 after programming in which filament 19 joins titanium layer 15 (FIG. 1D) and polysilicon layer 11. Note that FIG. 2A illustrates an edge 21 of amorphous silicon layer 14 that contacts polycrystalline silicon layer 11. As described above, stress relaxation occurs within amorphous silicon layer 14, not at its boundaries. Therefore, referring to FIG. 2B, if shearing occurs in prior art antifuse 20 due to stress relaxation, the sheared portion 19' of filament 19 significantly reduces the surface area 19A for conducting current, thereby resulting in instability of the resistance provided by antifuse 20.
Therefore, a need arises for an antifuse which programs at a relatively low programming voltage and ensures a stable resistance irrespective of shearing conditions.